High-bandwidth memory (HBM) sales are spiking as the amount of data that needs to be processed quickly by state-of-the-art AI ...

Panel-level packaging offers scalability and cost efficiency, but meeting advanced node process targets remains a formidable ...

A discussion with Jay Vleeschhouwer of Griffin Securities on EDA's continued consolidation, expansion into engineering ...

UCIe helps test through a fixed shoreline, multiple redundant lanes, and mission mode lane performance monitoring.

Device design begins with the anticipated workload. What is it actually supposed to do? What resources — computational units, ...

Factors that impact mask lifetime, the future role of actinic inspection, and minimum mask dimensions for high-NA EUV.

A new IEEE technical paper titled “Package Assembly Design Kits (PADK’s)- The Future of Advanced Wafer-Level Manufacturing” ...

Challenges and options vary widely depending on markets, workloads, and economics.

Siemens’ Jonathan Muirhead explains why matching and symmetry are so important for analog and RF circuits, especially in topological structures like differential pairs and current mirrors, and ...

Why microarchitectures and custom coding on low-cost chips are a growing source of concern.

Researchers from Queen Mary University of London created biodegradable, flexible, and electrically conductive nanocomposite ...